1. Field of the Invention
The present invention pertains to the field of computer systems. More particularly, this invention relates to an architecture for the speculative resource files and committed resource files in a processor employing speculative and out of order instruction execution.
2. Background
Typical prior computer processors implement in-order instruction execution pipelines. An in-order processor usually fetches an instruction stream from an external memory, and executes the instructions in a sequential program order. Such in-order processing of the instruction stream ensures that the data dependencies of the instructions are strictly observed during execution.
For example, instructions in the instruction stream commonly use the results of previous instructions as source data. The in-order execution of the instruction stream ensures that the previous instructions execute and provide the proper source data before execution of the subsequent instructions that require the source data.
A processor may implement an out of order instruction execution pipeline to increase instruction execution performance. Such a processor executes ready instructions in the instruction stream ahead of earlier instructions that are not ready. A ready instruction is typically an instruction having fully assembled source data.
Such out of order execution improves processor performance because the instruction execution pipeline of the processor does not stall while assembling source data for a non ready instruction. For example, a non ready instruction awaiting source data from an external memory fetch does not stall the execution of later instructions in the instruction stream that are ready to execute.
Some out of order processors may fetch a macroinstruction stream from an external memory, and convert each macroinstruction of the incoming stream into a set of micro instructions in a sequential program order. Such an out of order processor then executes the micro instructions according to the availability of source data and execution resources rather than the program order.
A processor may also implement a speculative instruction execution pipeline to increase instruction execution performance. A processor having speculative instruction execution typically determines a speculative execution path through a program by predicting the outcome of conditional branch instructions. Such a processor fetches an instruction stream from an external memory, predicts whether conditional branch instructions in the instruction stream will result in a branch, and continues fetching and executing the instruction stream according to the prediction. Such speculative execution increases processor performance because the instruction execution pipeline does not stall during the resolution of conditional branch instructions.
A processor that implements an out of order instruction execution pipeline along with speculative instruction execution generates out of order speculative result data for each micro instruction. The result data is out of order because the micro-instructions that cause generation of the result data are executed out of order. The result data is speculative until the branch prediction that caused speculative execution of the corresponding micro instruction is resolved. The branch prediction is resolved by comparing the prediction with a result of the conditional branch instruction. The result data for a micro instruction is also speculative until program exceptions for the corresponding macroinstruction are resolved. Program exceptions may include, for example, memory address space violations.
Such a speculative out of order processor may implement a reorder register file to buffer the speculative result data until the branch condition and program exceptions are resolved. The speculative result data in the reorder register file is discarded if a branch was mispredicted or if a program exception occurs. The speculative result data in the reorder register file is committed to the architectural state according to the Intel Microprocessor Architecture if the branch was correctly predicted and if a program exception does not occur. The reorder register file may also reimpose the original program order on the result data.
The architecture of such a reorder register file in a speculative out of order processor embodies a balance between the complexity of managing the speculative and committed status of the result data and the integrated circuit chip area required to implement the reorder register file.
For example, if the reorder register file buffers both speculative and committed result data, then the task of managing the speculative and committed status of each register in the reorder register file is relatively complex. On the other hand, such a reorder register file that buffers both speculative and committed result data minimizes the processor chip area because each register in the reorder register file performs dual functions.
Also, a typical prior processor implements separate integer and floating-point register files because floating-point data values usually require wider registers and data paths in comparison to integer data values. A prior speculative out-of-order processor would require implementation of an integer reorder register file for the speculative and committed integer result data and a floating-point reorder register file for the speculative and committed floating-point result data. Such separate integer and floating-point reorder register files increases the processor chip area. Such an increase in processor chip area increases the manufacturing cost of the processor.